VHDL Simulation of DWT for Low Level Image Processing Application

Discrete wavelet transform (DWT) is the one of the main approaches used for image compression. A new discrete wavelet transform (DWT) architecture is proposed in this paper to realize a memory-efficient 2D DWT unit. The main goal of the proposed system is to change the processing unit in the pipelined DWT. Processing unit is modified in such a way that total number of processing required in the system will be reduced. The hardware is efficiently reduced by using the concept of intra-stage parallelism and inter-stage parallelism. The intra-stage parallelism is obtained by dividing the 2D filtering operation into four tasks. The multi decomposition levels in the stage of pipeline are mapped by computational task in inter-stage parallelism. To maintain the critical path delay serially concatenated additions are optimized by changing computation topology and applying arithmetic optimization. The Proposed architecture computes DWT efficiently with less clock cycles. The hardware complexity of 2D DWT is significantly reduced.